module ext(
  input  [31:0] in,
  input  [ 1:0] op,
  input  [ 1:0] rot,
  input         sign_n,
  output [31:0] out
);

reg  [31:0] in_rot;
wire [31:0] extb, exth, extx;
wire        sign;

always @* begin
  case (rot)
    2'b00: in_rot =  in;
    2'b01: in_rot = {in[ 7:0], in[31: 8]};
    2'b10: in_rot = {in[15:0], in[31:16]};
    2'b11: in_rot = {in[23:0], in[31:24]};
  endcase
end

assign sign = ~sign_n;
assign extb = {{24{sign&in_rot[ 7]}}, in_rot[ 7: 0]};
assign exth = {{16{sign&in_rot[15]}}, in_rot[15: 0]};
assign extx = {{ 8{sign&in_rot[23]}}, in_rot[23:16],
               { 8{sign&in_rot[ 7]}}, in_rot[ 7: 0]};

assign out = op[0] ? exth : op[1] ? extb : extx;

endmodule
